COEVO Beats Every Rival by Fixing Buggy Chip Designs While Optimizing Them
COEVO unifies correctness and PPA optimization into a single evolutionary loop for LLM-based RTL generation . Correctness becomes a continuous fitness dimension, not a binary gate that discards promising buggy candidates.
Takeaways
- COEVO unifies correctness and PPA optimization into a single evolutionary loop for LLM-based RTL generation .
- Correctness becomes a continuous fitness dimension, not a binary gate that discards promising buggy candidates.
- Four-dimensional Pareto sorting over correctness, area, delay, and power removes manual weight tuning.
- Adaptive correctness gate with annealing lets partially correct designs guide early exploration.
- Hits 97.5% Pass@1 on VerilogEval 2.0 and 94.5% on RTLLM 2.0 with GPT-5.4-mini.
- Wins best PPA on 43 of 49 synthesizable RTLLM designs across four LLM backbones.
LLM-based Verilog pipelines often separate hardware generation into two stages: achieve functional correctness, then optimize power, performance, and area. The COEVO paper combines those goals in one evolutionary search, allowing partially correct designs with promising microarchitectures to remain in the population while their bugs are repaired.
Using GPT-5.4-mini, the authors report 97.5% Pass@1 on VerilogEval 2.0 and 94.5% on RTLLM 2.0. Pass@1 measures the share of tasks solved with one generated candidate. COEVO also produced the best reported PPA result on 43 of 49 synthesizable RTLLM designs and outperformed every agentic baseline evaluated across four LLM backbones.
Why staged search drops useful RTL
Register-transfer level code describes the registers, data paths, and control logic that form a digital circuit. Synthesis tools convert that RTL into a gate-level netlist, where engineers measure silicon area, critical-path delay, and power consumption. Lower delay can support a higher clock frequency. RTLLM 2.0 and VerilogEval 2.0 test generated RTL through compilation and functional simulation, while RTLLM also evaluates implementation quality through synthesis and layout.
Common agentic workflows ask one model or agent to write RTL, another to repair functional failures, and a later stage to improve PPA. Evolutionary variants frequently apply a hard functional gate before considering implementation quality. Both approaches can narrow the search around an early architecture before the optimizer sees alternatives with better hardware characteristics.
Reporting is indexed from AlphaSignal. Rights remain with the original publisher and cited sources.
Read original report
